1. Field of the Invention
The present invention relates in general to semiconductor memories, and more particularly, to improved output buffer circuitry for semiconductor memories.
2. Description of Related Arts
Today's semiconductor memory devices include more than hundreds of millions of memory cells. A basic function of the semiconductor memory device is to input and output data for the purpose of writing the data on such memory cells and reading the written data. To increase speed of operation, a class of semiconductor memory device has evolved from a synchronous dynamic random access memory (SDRAM) device to a double data rate (DDR) RAM device to a DDR II RAM device. Despite this evolution, there has not been a great change in the basic operation of the semiconductor memory device such as a refresh operation for refreshing each memory cell, or data input and output (I/O) operation for transmitting data between an external circuit and an internal circuit.
The above basic and unique function will be maintained even in a next generation semiconductor memory technology aimed to write or read data in high-speed and reduce manufacturing costs.
FIG. 1 is a block diagram showing a conventional semiconductor memory device.
The semiconductor memory device includes: a command and address control circuit 102, a row decoder 103, a column decoder 104, a memory array or cell area 105, an input/output driver 106, a data input buffer 107, a data input register 108, a data output register 109, and a data output buffer 110.
The command and address control circuit 102 receives a command COMM and an address ADDR from an external circuit such as a microprocessor and transmits the address ADDR to the row decoder 103 and to the column decoder 104. Also, the command and address control circuit 102 controls the row decoder 103, the column decoder 104, the data input buffer 107, the data input register 108, the data output register 109, and the data output buffer 110 in response to the inputted command COMM.
The cell area 105 includes a plurality of memory cells for storing a data and sense amplifiers for amplifying stored data. The row decoder 103 and the column decoder 104 select a memory cell to be read and written corresponding to the command COMM and the address ADDR inputted from the external circuit. Herein, the command COMM includes a plurality of instructions responsible for a row access and a column access in operation of the DRAM device. A row address strobe (RAS) signal, a column address strobe (CAS) signal and a write enable (WE) signal are examples of such instructions. Likewise, the address ADDR includes a row address and a column address for accessing a memory cell.
Hereinafter, operation of the semiconductor memory device will be described in detail. Once the RAS signal is activated, the row address is inputted. The row decoder 103 decodes the row address, and then, a number of the memory cells corresponding to the decoded address are activated. A data having a low potential stored within the activated memory cells is amplified by the sense amplifiers of the cell area 105. The sense amplifier is ready for a write operation or a read operation after amplifying the accessed data, i.e., the data stored within the activated memory cells. That is, the sense amplifiers can serve as a data cache for temporarily storing data.
In case of a read operation, once the CAS signal is activated, the column address is decoded and the data stored into a part of the sense amplifiers serving as the data cache is outputted to an internal data bus. The outputted data is stored into the data output register 109. The data stored into the data output register 109 is outputted after a predetermined time through the data output buffer 110.
FIG. 2 is a schematic circuit diagram describing the data output buffer 110. When a data clock signal DCLK is inputted under a state that an output enable signal OE is activated, a phase of a data signal DATA is determined and then, the data signal DATA is outputted to the input/output driver 106 shown in FIG. 1. At this time, a slope of the outputted signal is called a slew rate. The slew rate is expressed with a specific unit, for instance, 3V/ns, meaning that a voltage level of a signal is activated from about 0 V to about 3 V for about 1 nanosecond. If a logic low level is about 0 V and a logic high level is about 3 V in the semiconductor memory device, it is easy to understand how long a data signal is changed from a logic low level to a logic high level.
Herein, a first resistor R1 and a second resistor R2 are a kind of passive devices for determining the slew rate. Although the slew rate can be determined by various types of devices, particularly the slew rate determined by resistors will be described in this drawing.
In a conventional design of a DRAM device, the slew rate is generally provided as a fixed value. Thus, if the slew rate is high, a quality of a signal is reduced by bounce noises, and if the slew rate is low, an access time is greatly variable, thereby resulting in the signal quality reduction. Herein, the signal quality can be regarded as a signal integrity. The signal is outputted for a predetermined period including a data generating period and a data setting period. Herein, the data generating period generally called a data window is a period for generating a voltage level of an inputted or outputted signal to be stably sensed or transmitted. The data storing period circuit a period for determining a voltage level of the inputted or outputted signal, e.g., the voltage level from a logic high to a logic low or a logic low to a logic high. Thus, a good signal integrity indicates that the data guaranteeing period is relatively longer.
FIG. 3A is a diagram showing a waveform of a data output signal in case of an unsuitable slew rate. As shown, the data output signal has large amounts of noises. On the other hand, FIG. 3B is a diagram showing a waveform of a data output signal in case of a preferable slew rate. As shown, the data output signal has a sufficient data window.
However, since the slew rate is provided as the fixed value when a DRAM device is designed and manufactured, it is impossible to adjust the slew rate in the DRAM device according to a generation speed, a power level and so on.